    IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC
INCLUDED_CYFITTERRV_INC EQU 1
    GET cydevicerv.inc
    GET cydevicerv_trm.inc

; ADC_DelSig_1_Ext_CP_Clk
ADC_DelSig_1_Ext_CP_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
ADC_DelSig_1_Ext_CP_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
ADC_DelSig_1_Ext_CP_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
ADC_DelSig_1_Ext_CP_Clk__CFG2_SRC_SEL_MASK EQU 0x07
ADC_DelSig_1_Ext_CP_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
ADC_DelSig_1_Ext_CP_Clk__PM_ACT_MSK EQU 0x01
ADC_DelSig_1_Ext_CP_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
ADC_DelSig_1_Ext_CP_Clk__PM_STBY_MSK EQU 0x01

; ADC_DelSig_1_theACLK
ADC_DelSig_1_theACLK__CFG0 EQU CYREG_CLKDIST_ACFG0_CFG0
ADC_DelSig_1_theACLK__CFG1 EQU CYREG_CLKDIST_ACFG0_CFG1
ADC_DelSig_1_theACLK__CFG2 EQU CYREG_CLKDIST_ACFG0_CFG2
ADC_DelSig_1_theACLK__CFG2_SRC_SEL_MASK EQU 0x07
ADC_DelSig_1_theACLK__CFG3 EQU CYREG_CLKDIST_ACFG0_CFG3
ADC_DelSig_1_theACLK__CFG3_PHASE_DLY_MASK EQU 0x0F
ADC_DelSig_1_theACLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG1
ADC_DelSig_1_theACLK__PM_ACT_MSK EQU 0x01
ADC_DelSig_1_theACLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG1
ADC_DelSig_1_theACLK__PM_STBY_MSK EQU 0x01

; LCD_Char_1_LCDPort
LCD_Char_1_LCDPort__0__MASK EQU 0x01
LCD_Char_1_LCDPort__0__PC EQU CYREG_PRT2_PC0
LCD_Char_1_LCDPort__0__PORT EQU 2
LCD_Char_1_LCDPort__0__SHIFT EQU 0
LCD_Char_1_LCDPort__1__MASK EQU 0x02
LCD_Char_1_LCDPort__1__PC EQU CYREG_PRT2_PC1
LCD_Char_1_LCDPort__1__PORT EQU 2
LCD_Char_1_LCDPort__1__SHIFT EQU 1
LCD_Char_1_LCDPort__2__MASK EQU 0x04
LCD_Char_1_LCDPort__2__PC EQU CYREG_PRT2_PC2
LCD_Char_1_LCDPort__2__PORT EQU 2
LCD_Char_1_LCDPort__2__SHIFT EQU 2
LCD_Char_1_LCDPort__3__MASK EQU 0x08
LCD_Char_1_LCDPort__3__PC EQU CYREG_PRT2_PC3
LCD_Char_1_LCDPort__3__PORT EQU 2
LCD_Char_1_LCDPort__3__SHIFT EQU 3
LCD_Char_1_LCDPort__4__MASK EQU 0x10
LCD_Char_1_LCDPort__4__PC EQU CYREG_PRT2_PC4
LCD_Char_1_LCDPort__4__PORT EQU 2
LCD_Char_1_LCDPort__4__SHIFT EQU 4
LCD_Char_1_LCDPort__5__MASK EQU 0x20
LCD_Char_1_LCDPort__5__PC EQU CYREG_PRT2_PC5
LCD_Char_1_LCDPort__5__PORT EQU 2
LCD_Char_1_LCDPort__5__SHIFT EQU 5
LCD_Char_1_LCDPort__6__MASK EQU 0x40
LCD_Char_1_LCDPort__6__PC EQU CYREG_PRT2_PC6
LCD_Char_1_LCDPort__6__PORT EQU 2
LCD_Char_1_LCDPort__6__SHIFT EQU 6
LCD_Char_1_LCDPort__AG EQU CYREG_PRT2_AG
LCD_Char_1_LCDPort__AMUX EQU CYREG_PRT2_AMUX
LCD_Char_1_LCDPort__BIE EQU CYREG_PRT2_BIE
LCD_Char_1_LCDPort__BIT_MASK EQU CYREG_PRT2_BIT_MASK
LCD_Char_1_LCDPort__BYP EQU CYREG_PRT2_BYP
LCD_Char_1_LCDPort__CTL EQU CYREG_PRT2_CTL
LCD_Char_1_LCDPort__DM0 EQU CYREG_PRT2_DM0
LCD_Char_1_LCDPort__DM1 EQU CYREG_PRT2_DM1
LCD_Char_1_LCDPort__DM2 EQU CYREG_PRT2_DM2
LCD_Char_1_LCDPort__DR EQU CYREG_PRT2_DR
LCD_Char_1_LCDPort__INP_DIS EQU CYREG_PRT2_INP_DIS
LCD_Char_1_LCDPort__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
LCD_Char_1_LCDPort__LCD_EN EQU CYREG_PRT2_LCD_EN
LCD_Char_1_LCDPort__MASK EQU 0x7F
LCD_Char_1_LCDPort__PORT EQU 2
LCD_Char_1_LCDPort__PRT EQU CYREG_PRT2_PRT
LCD_Char_1_LCDPort__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
LCD_Char_1_LCDPort__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
LCD_Char_1_LCDPort__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
LCD_Char_1_LCDPort__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
LCD_Char_1_LCDPort__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
LCD_Char_1_LCDPort__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
LCD_Char_1_LCDPort__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
LCD_Char_1_LCDPort__PS EQU CYREG_PRT2_PS
LCD_Char_1_LCDPort__SHIFT EQU 0
LCD_Char_1_LCDPort__SLW EQU CYREG_PRT2_SLW

; ADC_DelSig_1_DSM2
ADC_DelSig_1_DSM2__BUF0 EQU CYREG_DSM0_BUF0
ADC_DelSig_1_DSM2__BUF1 EQU CYREG_DSM0_BUF1
ADC_DelSig_1_DSM2__BUF2 EQU CYREG_DSM0_BUF2
ADC_DelSig_1_DSM2__BUF3 EQU CYREG_DSM0_BUF3
ADC_DelSig_1_DSM2__CLK EQU CYREG_DSM0_CLK
ADC_DelSig_1_DSM2__CR0 EQU CYREG_DSM0_CR0
ADC_DelSig_1_DSM2__CR1 EQU CYREG_DSM0_CR1
ADC_DelSig_1_DSM2__CR10 EQU CYREG_DSM0_CR10
ADC_DelSig_1_DSM2__CR11 EQU CYREG_DSM0_CR11
ADC_DelSig_1_DSM2__CR12 EQU CYREG_DSM0_CR12
ADC_DelSig_1_DSM2__CR13 EQU CYREG_DSM0_CR13
ADC_DelSig_1_DSM2__CR14 EQU CYREG_DSM0_CR14
ADC_DelSig_1_DSM2__CR15 EQU CYREG_DSM0_CR15
ADC_DelSig_1_DSM2__CR16 EQU CYREG_DSM0_CR16
ADC_DelSig_1_DSM2__CR17 EQU CYREG_DSM0_CR17
ADC_DelSig_1_DSM2__CR2 EQU CYREG_DSM0_CR2
ADC_DelSig_1_DSM2__CR3 EQU CYREG_DSM0_CR3
ADC_DelSig_1_DSM2__CR4 EQU CYREG_DSM0_CR4
ADC_DelSig_1_DSM2__CR5 EQU CYREG_DSM0_CR5
ADC_DelSig_1_DSM2__CR6 EQU CYREG_DSM0_CR6
ADC_DelSig_1_DSM2__CR7 EQU CYREG_DSM0_CR7
ADC_DelSig_1_DSM2__CR8 EQU CYREG_DSM0_CR8
ADC_DelSig_1_DSM2__CR9 EQU CYREG_DSM0_CR9
ADC_DelSig_1_DSM2__DEM0 EQU CYREG_DSM0_DEM0
ADC_DelSig_1_DSM2__DEM1 EQU CYREG_DSM0_DEM1
ADC_DelSig_1_DSM2__MISC EQU CYREG_DSM0_MISC
ADC_DelSig_1_DSM2__OUT0 EQU CYREG_DSM0_OUT0
ADC_DelSig_1_DSM2__OUT1 EQU CYREG_DSM0_OUT1
ADC_DelSig_1_DSM2__REF0 EQU CYREG_DSM0_REF0
ADC_DelSig_1_DSM2__REF1 EQU CYREG_DSM0_REF1
ADC_DelSig_1_DSM2__REF2 EQU CYREG_DSM0_REF2
ADC_DelSig_1_DSM2__REF3 EQU CYREG_DSM0_REF3
ADC_DelSig_1_DSM2__RSVD1 EQU CYREG_DSM0_RSVD1
ADC_DelSig_1_DSM2__SW0 EQU CYREG_DSM0_SW0
ADC_DelSig_1_DSM2__SW2 EQU CYREG_DSM0_SW2
ADC_DelSig_1_DSM2__SW3 EQU CYREG_DSM0_SW3
ADC_DelSig_1_DSM2__SW4 EQU CYREG_DSM0_SW4
ADC_DelSig_1_DSM2__SW6 EQU CYREG_DSM0_SW6
ADC_DelSig_1_DSM2__TR0 EQU CYREG_NPUMP_DSM_TR0
ADC_DelSig_1_DSM2__TST0 EQU CYREG_DSM0_TST0
ADC_DelSig_1_DSM2__TST1 EQU CYREG_DSM0_TST1

; ADC_DelSig_1_DEC
ADC_DelSig_1_DEC__COHER EQU CYREG_DEC_COHER
ADC_DelSig_1_DEC__CR EQU CYREG_DEC_CR
ADC_DelSig_1_DEC__DR1 EQU CYREG_DEC_DR1
ADC_DelSig_1_DEC__DR2 EQU CYREG_DEC_DR2
ADC_DelSig_1_DEC__DR2H EQU CYREG_DEC_DR2H
ADC_DelSig_1_DEC__GCOR EQU CYREG_DEC_GCOR
ADC_DelSig_1_DEC__GCORH EQU CYREG_DEC_GCORH
ADC_DelSig_1_DEC__GVAL EQU CYREG_DEC_GVAL
ADC_DelSig_1_DEC__OCOR EQU CYREG_DEC_OCOR
ADC_DelSig_1_DEC__OCORH EQU CYREG_DEC_OCORH
ADC_DelSig_1_DEC__OCORM EQU CYREG_DEC_OCORM
ADC_DelSig_1_DEC__OUTSAMP EQU CYREG_DEC_OUTSAMP
ADC_DelSig_1_DEC__OUTSAMPH EQU CYREG_DEC_OUTSAMPH
ADC_DelSig_1_DEC__OUTSAMPM EQU CYREG_DEC_OUTSAMPM
ADC_DelSig_1_DEC__OUTSAMPS EQU CYREG_DEC_OUTSAMPS
ADC_DelSig_1_DEC__PM_ACT_CFG EQU CYREG_PM_ACT_CFG10
ADC_DelSig_1_DEC__PM_ACT_MSK EQU 0x01
ADC_DelSig_1_DEC__PM_STBY_CFG EQU CYREG_PM_STBY_CFG10
ADC_DelSig_1_DEC__PM_STBY_MSK EQU 0x01
ADC_DelSig_1_DEC__SHIFT1 EQU CYREG_DEC_SHIFT1
ADC_DelSig_1_DEC__SHIFT2 EQU CYREG_DEC_SHIFT2
ADC_DelSig_1_DEC__SR EQU CYREG_DEC_SR
ADC_DelSig_1_DEC__TRIM__16H EQU CYREG_FLSHID_CUST_TABLES_DEC_16H
ADC_DelSig_1_DEC__TRIM__16L EQU CYREG_FLSHID_CUST_TABLES_DEC_16L
ADC_DelSig_1_DEC__TRIM__1H EQU CYREG_FLSHID_CUST_TABLES_DEC_1H
ADC_DelSig_1_DEC__TRIM__1L EQU CYREG_FLSHID_CUST_TABLES_DEC_1L
ADC_DelSig_1_DEC__TRIM__4H EQU CYREG_FLSHID_CUST_TABLES_DEC_4H
ADC_DelSig_1_DEC__TRIM__4L EQU CYREG_FLSHID_CUST_TABLES_DEC_4L
ADC_DelSig_1_DEC__TRIM__P25H EQU CYREG_FLSHID_CUST_TABLES_DEC_P25H
ADC_DelSig_1_DEC__TRIM__P25L EQU CYREG_FLSHID_CUST_TABLES_DEC_P25L

; ADC_DelSig_1_IRQ
ADC_DelSig_1_IRQ__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
ADC_DelSig_1_IRQ__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
ADC_DelSig_1_IRQ__INTC_MASK EQU 0x20000000
ADC_DelSig_1_IRQ__INTC_NUMBER EQU 29
ADC_DelSig_1_IRQ__INTC_PRIOR_NUM EQU 7
ADC_DelSig_1_IRQ__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_29
ADC_DelSig_1_IRQ__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
ADC_DelSig_1_IRQ__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; Pin_1
Pin_1__0__MASK EQU 0x01
Pin_1__0__PC EQU CYREG_PRT0_PC0
Pin_1__0__PORT EQU 0
Pin_1__0__SHIFT EQU 0
Pin_1__AG EQU CYREG_PRT0_AG
Pin_1__AMUX EQU CYREG_PRT0_AMUX
Pin_1__BIE EQU CYREG_PRT0_BIE
Pin_1__BIT_MASK EQU CYREG_PRT0_BIT_MASK
Pin_1__BYP EQU CYREG_PRT0_BYP
Pin_1__CTL EQU CYREG_PRT0_CTL
Pin_1__DM0 EQU CYREG_PRT0_DM0
Pin_1__DM1 EQU CYREG_PRT0_DM1
Pin_1__DM2 EQU CYREG_PRT0_DM2
Pin_1__DR EQU CYREG_PRT0_DR
Pin_1__INP_DIS EQU CYREG_PRT0_INP_DIS
Pin_1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
Pin_1__LCD_EN EQU CYREG_PRT0_LCD_EN
Pin_1__PORT EQU 0
Pin_1__PRT EQU CYREG_PRT0_PRT
Pin_1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
Pin_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
Pin_1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
Pin_1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
Pin_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
Pin_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
Pin_1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
Pin_1__PS EQU CYREG_PRT0_PS
Pin_1__SLW EQU CYREG_PRT0_SLW

; Miscellaneous
; -- WARNING: define names containting LEOPARD or PANTHER are deprecated and will be removed in a future release
CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIG_FASTBOOT_ENABLED EQU 0
CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_MEMBER_5A EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_DIE_PANTHER EQU 2
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PANTHER
CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0
BCLK__BUS_CLK__HZ EQU 24000000
BCLK__BUS_CLK__KHZ EQU 24000
BCLK__BUS_CLK__MHZ EQU 24
CYDEV_APPLICATION_ID EQU 0x0000
CYDEV_APPLICATION_VERSION EQU 0x0000
CYDEV_BOOTLOADER_CHECKSUM EQU CYDEV_BOOTLOADER_CHECKSUM_BASIC
CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1
CYDEV_BOOTLOADER_FAST_VERIFY EQU 0
CYDEV_BOOTLOADER_VERSION EQU 0x0000
CYDEV_BOOTLOADER_WAIT_COMMAND EQU 1
CYDEV_BOOTLOADER_WAIT_TIME EQU 200
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x0E13C069
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5A
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5A_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PANTHER_PRODUCTION
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
CYDEV_CONFIGURATION_COMPRESSED EQU 0
CYDEV_CONFIGURATION_DMA EQU 1
CYDEV_CONFIGURATION_ECC EQU 1
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_DMA
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CUSTOM_ID EQU 0x00000000
CYDEV_DATA_CACHE_ENABLED EQU 0
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_REQXRES EQU 1
CYDEV_DEBUGGING_XRES EQU 0
CYDEV_DEBUG_ENABLE_MASK EQU 0x01
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DBG_DBE
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x1000
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
CYDEV_STACK_SIZE EQU 0x4000
CYDEV_VDDA_MV EQU 5000
CYDEV_VDDD_MV EQU 5000
CYDEV_VDDIO0_MV EQU 5000
CYDEV_VDDIO1_MV EQU 5000
CYDEV_VDDIO2_MV EQU 5000
CYDEV_VDDIO3_MV EQU 5000
CYDEV_VIO0 EQU 5
CYDEV_VIO0_MV EQU 5000
CYDEV_VIO1 EQU 5
CYDEV_VIO1_MV EQU 5000
CYDEV_VIO2 EQU 5
CYDEV_VIO2_MV EQU 5000
CYDEV_VIO3 EQU 5
CYDEV_VIO3_MV EQU 5000
CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
DMA_CHANNELS_USED__MASK0 EQU 0x00000000
CYDEV_BOOTLOADER_ENABLE EQU 0
    ENDIF
    END
